ECONOMIC EFFICIENCY OF VOLTAGE AND TEMPERATURE DRIFT COMPENSATION CIRCUIT FOR DIGITAL DELAY LINE

Abstract

Nowadays when semiconductor devices sizes reached to the few nanometers, high-speed SERDES systems became less power-consuming, and systems operating frequen-cies reached dozens of gigahertz. Despite these advantages, devices became more vulne-rable against temperature-voltage drifts. Also, because of dozens of gigahertz frequency data transmission, it became more complicated to meet timing constraints in Serdes sys-tems. Therefore, it is important to have stable de-skew mechanisms, otherwise data loss and other timing issues can be observed. One of the commonly used circuits to over-come this problem is digital delay lines (DDL). Often integrated circuits (IC) being used in non-standard environments, so it is necessity to have voltage-temperature (VT) compensation circuit (VTDCC), otherwise DDL will lose its effectiveness. The development of the proposed of VTDCC has become an economically important condition, because VTDCC allows digital delay line (DDL) to work correctly in non-standard conditions, which increases the demand for DDL. Digital delay line with included compensation circuit has shown around 51% DDL delay range improvement during non-standard conditions VT drift compensation circuit requires an additional 37% area in DDL.