Dynamic power-gating for leakage power reduction in FPGAs
Author:
Publisher
Zhejiang University Press
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing
Link
https://link.springer.com/content/pdf/10.1631/FITEE.2200084.pdf
Reference52 articles.
1. Ahmed I, Zhao SZ, Trescases O, et al., 2018. Automatic application-specific calibration to enable dynamic voltage scaling in FPGAs. IEEE Trans Comput-Aided Des Integr Circ Syst, 37(12):3095–3108. https://doi.org/10.1109/TCAD.2018.2801222
2. Ahmed I, Shen JL, Betz V, 2020. Optimizing FPGA logic circuitry for variable voltage supplies. IEEE Trans Very Large Scale Integr Syst, 28(4):890–903. https://doi.org/10.1109/TVLSI.2019.2962501
3. Ahmed R, Bsoul AAM, Wilton SJE, et al., 2014. High-level synthesis-based design methodology for dynamic power-gated FPGA. Proc 24th Int Conf on Field Programmable Logic and Applications, p.1–4. https://doi.org/10.1109/FPL.2014.6927433
4. Ahmed R, Wilton SJE, Hallschmid P, et al., 2015. Hierarchical dynamic power-gating in FPGAs. Proc 11th Int Symp on Applied Reconfigurable Computing, p.27–38. https://doi.org/10.1007/978-3-319-16214-0_3
5. Amara A, Amiel F, Ea T, 2006. FPGA vs. ASIC for low power applications. Microelectron J, 37(8):669–677. https://doi.org/10.1016/j.mejo.2005.11.003
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