High-speed, fixed-latency serial links with Xilinx FPGAs
Author:
Publisher
Zhejiang University Press
Subject
General Engineering
Link
http://link.springer.com/content/pdf/10.1631/jzus.C1300249.pdf
Reference16 articles.
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2. Aloisio, A., Cevenini, F., Giordano, R., et al., 2009. Highspeed, fixed-latency serial links with FPGAs for synchronous transfers. IEEE Trans. Nucl. Sci., 56(5):2864–2873. [doi:10.1109/TNS.2009.2027236]
3. Aloisio, A., Cevenini, F., Giordano, R., et al., 2010. Emulating the GLink chip set with FPGA serial transceivers in the ATLAS Level-1 Muon trigger. IEEE Trans. Nucl. Sci., 57(2):467–471. [doi:10.1109/TNS.2009.2036175]
4. Aloisio, A., Ameli, F., Bocci, V., et al., 2013. Design, implementation and test of the timing trigger and control receiver for the LHC. J. Instrum., 8(2):T02003. [doi:10. 1088/1748-0221/8/02/T02003]
5. Giordano, R., Aloisio, A., 2011. Fixed-latency, multi-gigabit serial links with Xilinx FPGAs. IEEE Trans. Nucl. Sci., 58(1):194–201. [doi:10.1109/TNS.2010.2101083]
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