Author:
Lv Jun-sheng,Li You,Zhou Yu-mei,Zhao Jian-zhong,Shen Hai-hua,Zhang Feng
Publisher
Zhejiang University Press
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing
Reference14 articles.
1. Abiri, B., Sheikholeslami, A., Tamura, H., et al., 2011. A 5Gb/s adaptive DFE for 2x blind ADC-based CDR in 65nm CMOS. IEEE Int. Solid-State Circuits Conf., p.436–438. http://dx.doi.org/10.1109/ISSCC.2011.5746386
2. Agrawal, A., Liu, A., Hanumolu, P.K., et al., 2009. An 8× 5 Gb/s parallel receiver with collaborative timing recovery. IEEE J. Sol.-State Circ., 44(11):3120–3130. http://dx.doi.org/10.1109/JSSC.2009.2033399
3. Anand, S.B., Razavi, B., 2001. A CMOS clock recovery circuit for 2.5-Gb/s NRZ data. IEEE J. Sol.-State Circ., 36(3):432–439. http://dx.doi.org/10.1109/4.910482
4. Coban, A.L., Koroglu, M.H., Ahmed, K.A., 2005. A 2.5-3.125-Gb/s quad transceiver with second-order analog DLLbased CDRs. IEEE J. Sol.-State Circ., 40(9):1940–1947. http://dx.doi.org/10.1109/JSSC.2005.848142
5. Kalantari, N., Buckwalter, J.F., 2013. A multichannel serial link receiver with dual-loop clock-and-data recovery and channel equalization. IEEE Trans. Circ. Syst. I, 60(11):2920–2931. http://dx.doi.org/10.1109/TCSI.2013.2256172