Circuit Reliability Prediction Based on Dual Autoencoders Combining Hash Coding and Partitioning Strategy
Author:
Publisher
China Science Publishing & Media Ltd.
Subject
Computer Graphics and Computer-Aided Design,Software
Link
https://engine.scichina.com/doi/pdf/8BBAB60230D944999DAE7D637739B705
Reference41 articles.
1. Diaz-Fortuny J, Martin-Martinez J, Rodriguez R, et al. CMOS characterization and compact modelling for circuit reliability simulation[C] //Proceedings of the 24th International Symposium on On-Line Testing and Robust System Design. Los Alamitos: IEEE Computer Society Press, 2018: 139-142.
2. Shu M H, Cheng C H, Chang J R. Using intuitionistic fuzzy sets for fault-tree analysis on printed circuit board assembly. Microelectronics Reliability, 2006, 46: 2139-2148.
3. Han J, Chen H, Liang J H. A stochastic computational approach for accurate and efficient reliability evaluation. IEEE Transactions on Computers, 2014, 63: 1336-1350.
4. Xiao J, Lee W, Jiang J H. Circuit reliability estimation based on an iterative PTM model with hybrid coding. Microelectronics Journal, 2016, 52: 117-123.
5. Zhang S H, Yang F, Zhou D, et al. An efficient asynchronous batch Bayesian optimization approach for analog circuit synthesis[C] //Proceedings of the 57th ACM/IEEE Design Automation Conference (DAC). Los Alamitos: IEEE Computer Society Press, 2020: 1-6.
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