The Accelerated 3D Capacitance Extraction Based on Adaptive Low-Rank Matrix Factorization
Author:
Publisher
China Science Publishing & Media Ltd.
Subject
Computer Graphics and Computer-Aided Design,Software
Link
https://engine.scichina.com/doi/pdf/B45FDFA6CE7C4C3A873D3EEEED9301C0
Reference21 articles.
1. Yu W J, Wang Z Y, Gu J C. Fast capacitance extraction of actual 3-D VLSI interconnects using quasi-multiple medium accelerated BEM. IEEE Transactions on Microwave Theory and Techniques, 2003, 51: 109-119.
2. Yu W J, Zhang M S, Wang Z Y. Efficient 3-D extraction of interconnect capacitance considering floating metal fills with boundary element method. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, 25: 12-18.
3. Nabors K, White J. Multipole-accelerated capacitance extraction algorithms for 3-D structures with multiple dielectrics. IEEE Transactions on Circuits and Systems I, 1992, 39: 946-954.
4. Zhou Y H, Nevels R D, Shi W P. Capacitance extraction with provably good absorbing boundary conditions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018, 37: 2013-2021.
5. Maffezzoni P, Zhang Z, Levantino S. Variation-aware modeling of integrated capacitors based on floating random walk extraction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018, 37: 2180-2184.
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