A 3D Interactive Visualization Program for Interconnect Capacitance Extraction of Integrated Circuits
Author:
Publisher
China Science Publishing & Media Ltd.
Subject
Computer Graphics and Computer-Aided Design,Software
Link
https://engine.scichina.com/doi/pdf/1E22E14C6FE4472485F578ABB8EAE89F
Reference18 articles.
1. Yu W J, Song M Y, Yang M. Advancements and challenges on parasitic extraction for advanced process technologies[C] //Proceedings of the 26th Asia and South Pacific Design Automation Conference. New York: ACM Press, 2021: 841-846.
2. le Coz Y L, Iverson R B. A stochastic algorithm for high speed capacitance extraction in integrated circuits. Solid-State Electronics, 1992, 35: 1005-1012.
3. Yu W J, Zhuang H, Zhang C. RWCap: a floating random walk solver for 3-D capacitance extraction of very-large-scale integration interconnects. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013, 32: 353-366.
4. Maffezzoni P, Zhang Z, Levantino S. Variation-aware modeling of integrated capacitors based on floating random walk extraction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018, 37: 2180-2184.
5. Wei X, Yan C H, Zhou H, et al. An efficient FPGA-based floating random walk solver for capacitance extraction using SDAccel[C] //Proceedings of the Design, Automation & Test in Europe Conference & Exhibition. Los Alamitos: IEEE Computer Society Press, 2019: 1040-1045.
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