Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency

Author:

Olukotun Kunle,Hammond Lance,Laudon James

Publisher

Morgan & Claypool Publishers LLC

Subject

Hardware and Architecture

Reference66 articles.

1. D. W. Wall , "Limits of instruction-level parallelism," WRL Research Report 93/6 ,Digital Western Research Laboratory,Palo Alto, CA,1993 .

2. K. Yeager , "R10 000 superscalar microprocessor ," presented atHot Chips VII,Stanford, CA,1995 .

3. B. A. Nayfeh, L. Hammond, and K. Olukotun , "Evaluating alternatives for a multiprocessor microprocessor ," inProceedings of 23rd Int. Symp. Computer Architecture,Philadelphia, PA,1996 , pp.66 -77 .

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