Electrical study of DSA shrink process and CD rectification effect at sub-60nm using EUV test vehicle
Author:
Affiliation:
1. IBM Corp. (United States)
2. TEL Technology Ctr., America, LLC (United States)
3. JSR Micro, Inc. (United States)
Publisher
SPIE
Reference15 articles.
1. C. T. Black, R. Ruiz, G. Breyta, J. Y, Cheng, M. C. Colburn, K. W. Guarini, and Y. Zhang, “Polymer Self Assembly in Semiconductor Microelectronics,” in IBM Journal of Research and Development, 2007, pp 605–633.
2. Implementation of templated DSA for via layer patterning at the 7nm node;Gronheid,2015
3. Process optimization of templated DSA flows;Gronheid,2014
4. High-volume manufacturing equipment and processing for directed self-assembly applications;Somervell,2014
5. DFM for defect-free DSA hole shrink process;Fukawatase,2014
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1. Negative-tone resists for EUV lithography;Advances in Patterning Materials and Processes XL;2023-05-01
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