Lithography-induced limits to scaling of design quality-Reference-Cited by-同舟云学术

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Lithography-induced limits to scaling of design quality

Published:2014-03-28 Issue: Volume: Page:
ISSN:0277-786X
Container-title:SPIE Proceedings
language:
Short-container-title:

Author:

Kahng Andrew B.

Publisher

SPIE

Reference46 articles.

1. Continuing to Shrink: Next-Generation Lithography – Progress and Prospects;Brink,2013

2. Tunable Sensors for Process-Aware Voltage Scaling;Chan,2012

3. Post-Routing Back-End-of-Line Layout Optimization for Improved Time-Dependent Dielectric Breakdown Reliability;Chan,2013

4. Double Patterning Design Split Implementation and Validation for the 32nm Node;Drapeau,2007

5. Pitch Doubling Through Dual-Patterning Lithography: Challenges in Integration and Litho Budgets;Dusa,2007

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4. Minimum Implant Area-Aware Placement and Threshold Voltage Refinement;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2017-07

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