Inspection of integrated circuit databases through reticle and wafer simulation: an integrated approach to design for manufacturing (DFM)

Author:

Howard William,Tirapu Azpiroz Jaione,Xiong Yalin,Mack Chris,Verma Gaurav,Volk William,Lehon Harold,Deng Yunfei,Shi Rui-fang,Culp James,Mansfield Scott

Publisher

SPIE

Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A 90 nm Static CMOS Technology Gate-Level Integrated Circuit Layout Classification and Error Detection Using EfficientNet Model;2020 IEEE 12th International Conference on Humanoid, Nanotechnology, Information Technology, Communication and Control, Environment, and Management (HNICEM);2020-12-03

2. Lithography-simulation-based design for manufacturability rule development: an integrated circuit design house’s approach;Journal of Micro/Nanolithography, MEMS, and MOEMS;2007-07-01

3. Through-process modeling for design-for-manufacturability applications;Journal of Micro/Nanolithography, MEMS, and MOEMS;2007-07-01

4. Investigation of DFM-lite ORC approach during OPC simulation;SPIE Proceedings;2007-03-16

5. Challenges and solutions for trench lithography beyond 65nm node;SPIE Proceedings;2006-03-10

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