Lithography and OPC friendly triple patterning decomposition method for VIA-Reference-Cited by-同舟云学术

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Lithography and OPC friendly triple patterning decomposition method for VIA

Published:2017-03-24 Issue: Volume: Page:
ISSN:0277-786X
Container-title:SPIE Proceedings
language:
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Author:

Yan Guanyong¹,Li Liang¹,Chen Xiao¹,Liu Qingwei¹,Tu Yuanying²

Affiliation:

1. Semiconductor Manufacturing International Corp. (China)

2. Mentor Graphics Corp. (United States)

Publisher

SPIE

Reference9 articles.

1. ASML, www.asml.com

2. International Technology Roadmap for Semiconductors, ITRS 2013, www.itrs.net

3. Characterization and Decomposition of Self-Aligned Quadruple Patterning Friendly Layout;Zhang,2012

4. Self-aligned triple patterning for continuous IC scaling to half-pitch 15nm;Chen,2011

5. An Efficient Auto TPT Stitch Guidance Generation for Optimized Standard Cell Design;Chary Samboju,2015

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