1. Single Lithography Exposure Edge Placement Model;Tyminski,2015
2. Double patterning process with freezing technique;Wakamatsu,2009
3. Evaluation of double-patterning techniques for advanced logic nodes;Koay,2010
4. 32nm logic patterning options with immersion lithography;Lai,2008
5. Wafer to Wafer Overlay Control Algorithm Implementation Based on Statistics;Lee,2015