Design-technology co-optimization of sequential and monolithic CFET as enabler of technology node beyond 2nm-Reference-Cited by-同舟云学术

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Design-technology co-optimization of sequential and monolithic CFET as enabler of technology node beyond 2nm

Published:2021-04-22 Issue: Volume: Page:
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Container-title:Design-Process-Technology Co-optimization XV
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Author:

Chehab Bilal,Ryckaert Julien,Schuddinck Pieter,Weckx Pieter,Horiguchi Naoto,Mirabelli Gioele,Spessot Alessio,Na Myunghee

Publisher

SPIE

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Active area patterning for CFET: nanosheet etch;Advanced Etch Technology and Process Integration for Nanopatterning XIII;2024-04-09

2. Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

3. CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark;IEEE Transactions on Electron Devices;2023-10

4. CFET SRAM DTCO, Interconnect Guideline, and Benchmark for CMOS Scaling;IEEE Transactions on Electron Devices;2023-03

5. Design, patterning, and process integration overview for 2nm node;DTCO and Computational Patterning;2022-05-26

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