Analysis of mix-and-match litho approach for manufacturing 20nm logic-node products-Reference-Cited by-同舟云学术

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Analysis of mix-and-match litho approach for manufacturing 20nm logic-node products

Published:2014-03-28 Issue: Volume: Page:
ISSN:0277-786X
Container-title:SPIE Proceedings
language:
Short-container-title:

Author:

Wei Yayi,Zhao Chao,Ye Tianchun

Publisher

SPIE

Reference8 articles.

1. See for example, International Technology Roadmap for Semiconductors, 2011 Edition.

2. Assessment of negative tone development challenges;Mehta,2012

3. Overlay Improvement Roadmap: Strategies for Scanner Control and Product Disposition for 5 nm overlay;Felix,2011

4. MAPPER: Progress towards a High Volume Manufacturing system;de Boer,2013

5. MAPPER Alignment sensor evaluation on Process Wafers;Vergeer,2013

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Directed self-assembly of block copolymers for sub-10 nm fabrication;International Journal of Extreme Manufacturing;2020-08-12

2. Analysis of multi-e-beam lithography for cutting layers at 7-nm node;Journal of Micro/Nanolithography, MEMS, and MOEMS;2016-10-14

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