Patterning performance of hyper NA immersion lithography for 32nm node logic process-Reference-Cited by-同舟云学术

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Patterning performance of hyper NA immersion lithography for 32nm node logic process

Published:2008-11-20 Issue: Volume: Page:
ISSN:0277-786X
Container-title:SPIE Proceedings
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Author:

Takahata Kazuhiro,Kajiwara Masanari,Kitamura Yosuke,Ojima Tomoko,Satake Masaki,Fujise Hiroharu,Seino Yuriko,Ema Tatsuhiko,Takakuwa Manabu,Nakagawa Shinichiro,Kono Takuya,Asano Masafumi,Kyo Suigen,Nomachi Akiko,Harakawa Hideaki,Ishida Tatsuya,Hasegawa Shunsuke,Miyashita Katsura,Murakami Takashi,Nagahara Seiji,Takeda Kazuhiro,Mimotogi Shoji,Inoue Soichi

Publisher

SPIE

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A study on the factors that affect the advanced mask defect verification;SPIE Proceedings;2015-10-23

2. Resist process control for 32-nm logic node and beyond with NA > 1.30 immersion exposure tool;Advances in Resist Materials and Processing Technology XXVI;2009-03-13

3. Advanced immersion contact hole patterning for sub 40nm memory applications: a fundamental resist study;Advances in Resist Materials and Processing Technology XXVI;2009-03-13

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