Pre-PDK block-level PPAC assessment of technology options for sub-7nm high-performance logic

Author:

Liebmann Lars W.,Gerousis Vassilios,Northrop Gregory,Facchini Marco,Riviere Lionel,Baum Zachary,Nakamoto Norihito,Chanemougame Daniel,Han Geng,Sun K.

Publisher

SPIE

Reference7 articles.

1. Low-track height standard-cell design in N5 using scaling boosters;Sherazi,2017

2. Overcoming scaling barriers through design technology CoOptimization

3. Low track height standard-cells enable high-placement density and low-BEOL cost in N5;Debacker,2017

4. The daunting complexity of scaling to 7NM without EUV: pushing DTCO to the extreme;Liebmann,2015

5. Exploiting regularity: breakthroughs in sub-7nm place-and-route;Liebmann,2017

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