1. Kasprowicz, G., Pastuszak, G., Poźniak, K., Trochimiuk, M., Abramowski, A., Gaska, M., Bukowiecka, D., Tyburska, A., Struniawski, J., Jastrzebski, P., Jewartowski, B., Frasunek, P., Nalbach-Moszynska, M., Brawata, S., Bubak, I., and Gloza, M., “Video signals integrator (vsi) system architecture,”
2. Xilinx, “Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit.” https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-es2-g.html.
3. Xilinx, “Vivado Design Suite - HLx Editions.” https://www.xilinx.com/products/design-tools/vivado.html.
4. A novel architecture of arithmetic coder in JPEG2000 based on parallel symbol encoding;Pastuszak,2004
5. Optimization of the Adaptive Computationally-Scalable Motion Estimation and Compensation for the Hardware H.264/AVC Encoder