Mapping stresses in high aspect ratio polysilicon electrical through-wafer interconnects-Reference-Cited by-同舟云学术

Mapping stresses in high aspect ratio polysilicon electrical through-wafer interconnects

Published:2015-06-17 Issue:2 Volume:14 Page:024001
ISSN:1932-5150
Container-title:Journal of Micro/Nanolithography, MEMS, and MOEMS
language:en
Short-container-title:J. Micro/Nanolith. MEMS MOEMS

Author:

Sharma Himani¹,Krabbe Joshua D.²,Farsinezhad Samira¹,van Popta Andy C.²,Wakefield Nick G.²,Fitzpatrick Glen A.²,Shankar Karthik³

Affiliation:

1. University of Alberta, Department of Electrical and Computer Engineering, Edmonton, Alberta T6G 2V4, Canada

2. Micralyne Inc., Edmonton, Alberta T6N 1E6, Canada

3. University of Alberta, Department of Electrical and Computer Engineering, Edmonton, Alberta T6G 2V4, CanadacNRC National Institute for Nanotechnology, Edmonton, Alberta T6G 2M9, Canada

Publisher

SPIE-Intl Soc Optical Eng

Subject

Electrical and Electronic Engineering,Mechanical Engineering,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference28 articles.

1. Process compatible polysilicon-based electrical through-wafer interconnects in silicon substrates

2. Impact of Near-Surface Thermal Stresses on Interfacial Reliability of Through-Silicon Vias for 3-D Interconnects

3. Micro-Raman spectroscopy and analysis of near-surface stresses in silicon around through-silicon vias for three-dimensional interconnects

4. Three-Dimensional Packaging Technology for Stacked DRAM With 3-Gb/s Data Transfer

5. Process compatible polysilicon-based electrical through-wafer interconnects in silicon substrates

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