Metal1 patterning study for random-logic applications with 193i, using calibrated OPC for litho and etch-Reference-Cited by-同舟云学术

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Metal1 patterning study for random-logic applications with 193i, using calibrated OPC for litho and etch

Published:2014-03-31 Issue: Volume: Page:
ISSN:0277-786X
Container-title:SPIE Proceedings
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Author:

Mailfert Julien,Van de Kerkhove Jeroen,De Bisschop Peter,De Meyer Kristin

Publisher

SPIE

Reference23 articles.

1. Litho and patterning challenges for memory and logic applications at the 22nm node;Finders,2010

2. Solutions for 22nm node patterning using ArFi technology;Finders,2011

3. Joint-optimization of layout and litho for SRAM and Logic towards the 20nm node, using 193i;Bisschop,2011

4. Computational study of line tip printability of sub-20nm technology;Yuan,2012

5. Lithographic challenges and their solutions for critical layers in sub-14nm node logic devices;Chiou,2013

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Vertical Surrounding Gate Transistor for High Density and Low Voltage Operation in DRAM;IEEE Access;2024

2. Novel approach of virtual etch target (VET) for efficient litho-to-etch pattern fidelity correction;DTCO and Computational Patterning;2022-05-26

3. Fast inverse lithography based on dual-channel model-driven deep learning;Optics Express;2020-06-24

4. Optical proximity correction: A cross road of data flows;Japanese Journal of Applied Physics;2016-05-31

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