Large feature wafer level in-line optical metrology techniques for advanced packaging schemes-Reference-Cited by-同舟云学术

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Large feature wafer level in-line optical metrology techniques for advanced packaging schemes

Published:2024-04-16 Issue: Volume:12955 Page:57
ISSN:
Container-title:Metrology, Inspection, and Process Control XXXVIII
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Author:

Sieg Katherine,Bottoms Christopher,Waskiewicz Christopher J.,Matos Mejia Alejandro,Han Junwon,Butt Shahid,Schmidt Daniel,Schoeche Stefan,Hamer Alexander,Hubbard Alex

Publisher

SPIE

Reference11 articles.

1. Multi-chip technologies to unleash computing performance gains over the next decade

2. “Chapter 1: HIR Overview and Executive Summary” IEEE Heterogeneous Integration Roadmap, 2019, [Online]. Available: http://eps.ieee.org/hir

3. Understanding Chiplets Today to Anticipate Future Integration Opportunities and Limits

4. 2.5D and 3D Heterogeneous Integration: Emerging applications

5. 2.5D/3D Integration Technologies for Circuit Obfuscation

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Spectral interferometry for TSV metrology in chiplet technology;Metrology, Inspection, and Process Control XXXVIII;2024-04-10

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