Field-programmable ring array employing AMZI-assisted-MRR structure for photonic signal processor

Author:

Sun Yaohui1ORCID,Wang Dongyu1ORCID,Wang Lihan2ORCID,Zhou Yue1ORCID,Pan Shilong2ORCID,Hu Guohua1ORCID,Yun Binfeng1ORCID,Cui Yiping1

Affiliation:

1. Advanced Photonics Center, School of Electronic Science and Engineering, Southeast University 1 , Nanjing 210096, People’s Republic of China

2. Key Laboratory of Radar Imaging and Microwave Photonics, Ministry of Education, Nanjing University of Aeronautics and Astronautics 2 , Nanjing 210016, People’s Republic of China

Abstract

A field-programmable photonic gate array is an integrated optical chip that combines electrical control and optical processing, enabling real-time reconfiguration of the optical path through software programming. While most current optical processors rely on Mach–Zehnder interferometer (MZI)-based architectures, those based on micro-disk resonators (MDRs) offer unique characteristics, including high integration and wavelength correlation, providing new ideas for programmable photonic chip architectures. In this paper, a scalable asymmetric MZI-assisted field-programmable micro-ring array (AMZI-FPRA) processor is proposed with a cell area of only 85 × 42 µm2. This design not only has high wavelength selectivity but also possesses dual adjustable wavelengths and coupling coefficients compared with traditional MDRs. By extending the cell into a 2 × 2 AMZI-FPRA using a two-dimensional square mesh approach, it is experimentally demonstrated that different optical path topologies can be realized with a compact footprint, including bandpass bandstop filtering, optical temporal differentiation, microwave delay, wavelength-division multiplexing/demultiplexing, and optical add-drop multiplexing. Increasing the array scale will enable more versatile and high-performance microwave photonic signal processing tasks. The scheme will be a promising candidate at the present time for reconfigurable programmable photonic signal processors due to its wide reconfigurability, on-chip integration, complementary metal–oxide–semiconductor-compatibility, and low power consumption.

Funder

National Natural Science Foundation of China

National Key Research and Development Program of China

Publisher

AIP Publishing

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