Area optimization of active reference band gap amplifier in cadence virtuoso

Author:

Sheng Tan Wei,Hussin Razaidi,Ismail Rizalafande Che,Isa Mohd Nazrin Md,Naziri Siti Zarina Md,Ahmad Norhawati,Isa Muammar Mohamad,Kamarudin Afzan

Publisher

AIP Publishing

Reference7 articles.

1. R. I. T. T. B. T. and A. S. P., "Bandgap Voltage Reference -Simulations in Cadence and Layout Design," ANNUAL JOURNAL OF ELECTRONICS, pp. 190–193, 2009.

2. A CMOS bandgap voltage reference

3. Design considerations of recent advanced low-voltage low-temperature-coefficient CMOS bandgap voltage reference

4. Eric Marsman, "Datapath Floorplanning and Routing in a Three Metal Layer Process," December 2001. [Online]. Available: https://my.eng.utah.edu/∼cs6710/handouts/floorplanning_3LM.pdf. [Accessed 19 April 2021].

5. "What are Vias & Why Do We Require Them While Designing a Printed Circuit Board (PCB)?," NewsWatch, 18 April 2021. [Online]. Available: https://newswatchtv.com/2018/06/19/vias-require-designing-printed-circuit-board-pcb/. [Accessed 19 April 2021].

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