A 6.6 ps RMS resolution time-to-digital converter using interleaved sampling method in a 28 nm FPGA
Author:
Affiliation:
1. School of Instrument Science and Opto-Electronics Engineering, Hefei University of Technology, Hefei, Anhui 230009, China
2. China Research Center of High Speed Machine Vision of Hefei i-Tek OptoElectronics Co., Ltd., Hefei, Anhui 230088, China
Funder
National Natural Science Foundation of China
Publisher
AIP Publishing
Subject
Instrumentation
Link
http://aip.scitation.org/doi/pdf/10.1063/1.5084014
Reference20 articles.
1. A 17ps time-to-digital converter implemented in 65nm FPGA technology
2. A high-resolution time-to-digital converter implemented in field-programmable-gate-arrays
3. The 10-ps Multitime Measurements Averaging TDC Implemented in an FPGA
4. Time-to-Digital Converter Based on FPGA With Multiple Channel Capability
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