1. Scalable load balancing congestion-aware Network-on-Chip router architecture
2. M. O. Gharan and G. N. Khan, “A Novel Virtual Channel Implementation Technique for Multi-Core On-Chip Communication,” in Proc. WAMCA, New York, NY, USA, 2012, pp. 36–41A.
3. A. Kumar, L.S. Peh, P. Kundu and N.K. Jha, “A 4.6 Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS”, International Conference on Computer Design, pp. 63–70, 2007.
4. G. Rajakumar, M. Prem Kumar, “Implementation and Path Selection under Budget Constraints Using CognitiveRadio Networks”, International Journal of Communication and Computer Technologies (IJCCT), 02, No.1, Issue 05, pp. 1–6, May 2014.
5. Robert Mullins, Andrew West and Simon “Moore Low-Latency Virtual-Channel Routers for On-Chip Networks.” in Computer Laboratory, University of Cambridge William Gates Building, JJ Thomson Avenue, Cambridge CB3 0FD, UK, pp. 89–96, 2008.