Carbon nanotube network film-based field-effect transistor interface state optimization by ambient air annealing

Author:

Hou Zhenfei1ORCID,Liu Yiwei2ORCID,Niu Gang3ORCID,Sun Yanxiao3ORCID,Li Jie1ORCID,Zhao Jinyan3,Wu Shengli1ORCID

Affiliation:

1. Key Laboratory for Physical Electronics and Devices of the Ministry of Education, School of Electronic Science and Engineering, Faculty of Electronic and Information Engineering, Xi’an Jiaotong University 1 , Xi’an 710049, China

2. Department of Physics, Hunan Institute of Advanced Sensing and Information Technology, Xiangtan University 2 , Xiangtan 411105, China

3. Electronic Materials Research Laboratory, Key Laboratory of the Ministry of Education, International Center for Dielectric Research, School of Electronic Science and Engineering, The International Joint Laboratory for Micro/Nano Manufacturing and Measurement Technology, Xi’an Jiaotong University 3 , Xi’an 710049, China

Abstract

Carbon nanotube field-effect transistors (CNTFETs) have been considered a strong candidate for post-Si era electronics due to the virtues of higher speed, lower power consumption, and multiple functionalities. The interface analysis based on the top gate structure has made little progress and lacks a reliable charge trap characterization model suitable for carbon tube devices. Quantitative extraction and analysis of the interface state are crucial for the integration of top-gate devices. Herein, a 5 nm thick Y2O3 thin film was selected as the gate dielectric layer in the top-gate CNTFETs device, and a post-annealing process in air ambience was utilized to optimize the Y2O3-CNT interface. A series of device performance evaluation results indicated that the post-annealing process in air ambience can effectively improve the on-state current and reduce the threshold voltage and subthreshold swing of the device, which are derived from diffusion of oxygen atom in the Y2O3 layer and optimization of the interface of Y2O3-CNT. Specifically, the maximum mobility, subthreshold swing, and threshold voltage are calculated to be 29 cm2/V s, 103 mV/dec, and −0.1 V, respectively, and the interface state density is reduced from 2.68 × 1012 to 1.51 × 1012 cm−2 in the gate insulator. These results not only are important to understand the dielectric impact on CNTFET devices but also are useful for future materials’ development and device optimization for high-performance CNT-based electronics.

Funder

National Key Research and Development Program of China

Publisher

AIP Publishing

Subject

General Physics and Astronomy

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