1. Efficient encoding of low-density parity-check codes
2. Stefan Scholl, Norbert When, “Efficient architectures for parity checkmatrix generation” Signal Processing and Information Technology (ISSPIT) 2016 IEEE International Symposium on, pp. 280–285, 2016.
3. Barry, Paton, (March 1998 Edition). Fundamentals of Digital Electronics (pp. 2–3). Dalhousie University.
4. Debalina Roy Choudhury, Krishanu Podder, “Design of Hamming CodeEncoding andDecodingCircuitUsingTransmissionGateLogic”, IRJET, volume:02, Issue: 07, Oct. 2015.
5. Parvez, A.S., Rahman, M.M., Podder, P., Hossain, M. and Islam, M.A., 2019. Design and implementation of hamming encoder and decoder over FPGA. In International Conference on Computer Networks and Communication Technologies (pp. 1005–1022). Springer, Singapore.