Influence of uniaxial strain in Si and Ge p-type double-gate metal-oxide-semiconductor field effect transistors
Author:
Publisher
AIP Publishing
Subject
General Physics and Astronomy
Link
http://aip.scitation.org/doi/pdf/10.1063/1.4930567
Reference31 articles.
1. Power-constrained CMOS scaling limits
2. A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 μm/sup 2/ SRAM cell
3. A 90-nm Logic Technology Featuring Strained-Silicon
4. Uniaxial-process-induced strained-Si: extending the CMOS roadmap
5. Performance Comparison of GaSb, Strained-Si, and InGaAs Double-Gate Ultrathin-Body n-FETs
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