Plan and development of efficient branch predictor for in-order RISC-V processor-Reference-Cited by-同舟云学术

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Plan and development of efficient branch predictor for in-order RISC-V processor

Published:2022 Issue: Volume: Page:
ISSN:0094-243X
Container-title:RECENT TRENDS IN SCIENCE AND ENGINEERING
language:
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Author:

Benila A.,Priyadharshini R. Indra,Slacer Priscilla Packia,Jacob J. Joyce,Theresa M. Mercy

Publisher

AIP Publishing

Link

http://aip.scitation.org/doi/pdf/10.1063/5.0074195

Reference39 articles.

1. T-Y. Yeh and Y.N. Patt, Technical Report CSE-TR-117-91, Computer Science & Engineering Division, Department of EECS, University of Michigan, (1991).

2. Reducing the cost of branches

3. Aneesh Raveendran, Vinayak Baramu Patil, David Selvakumar, Vivian Desalphine International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) (2016)

4. Smith, Jim E.: Int. Symposium on Computer Architecture, 135–148 (1981)

5. Yeh, Tse-Yu, and Yale N. Patt: Int. Symposium on Computer Architecture, 257–266 (1993)

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