Tunable electrocaloric effect in selective ferroelectric bilayers via electrostatics for solid-state refrigeration and microelectronics thermal management

Abstract

Ferroelectric (FE) electrocaloric materials research has been blossoming worldwide for solid-state refrigeration and potential cooling systems replacing thermoelectric Peltier coolers in microelectronics. In this work, we report the outcomes from a systematic study of combined phase transition (thermodynamics) based on the phenomenological Landau theory and distributed electric field (electrostatics of thin film interfaces) in FE bilayer films. Specifically, the compositional variation of ferroelectric bilayers results in broken spatial inversion symmetry leading to asymmetric thermodynamic potentials due to a combination of normal (first- and second-order phase transition) and relaxor (dispersive dielectric constant) ferroelectric behaviors devised for efficient electrocaloric cooling effects. Extensive theoretical analyses conducted for bilayers consisting of insulating materials highlight modified phase transition temperature behavior and self-poling by effective electric field amplification arising due to bilayers’ electrostatic coupling yielding significant changes in isothermal entropy (ΔS) and adiabatic temperature (ΔT). The theoretical calculation insights supported with experimental results signify, through case studies for a combination of materials experimental parameters, that amplification of the local electric field and materials engineering maximize the number of coexisting phases at or away from the morphotropic phase boundary of constituent layers in bilayer thin film architectures, which can be applicable toward other classes of materials and multilayer systems. These are effective ways for efficient cooling, in general, and for microelectronics thermal management either directly or by developing a thermal switch with phase change materials integrated with thermoelectric coolers for residual heat dissipation, both at the system and on-chip levels.