Direct strain measurement in a 65nm node strained silicon transistor by convergent-beam electron diffraction
Author:
Publisher
AIP Publishing
Subject
Physics and Astronomy (miscellaneous)
Link
http://aip.scitation.org/doi/pdf/10.1063/1.2362978
Reference17 articles.
1. A Logic Nanotechnology Featuring Strained-Silicon
2. A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell
3. Mobility enhancement
4. Electron Microdiffraction
5. Automated lattice parameter measurement from HOLZ lines and their use for the measurement of oxygen content in YBa2Cu3O7-δ from nanometer-sized region
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