Evaluation of interface traps inside the conduction band of InAs-on-insulator nMOSFET by self-consistent Hall-QSCV method
Author:
Affiliation:
1. Department of Electrical Engineering and Information Systems, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo, Japan
Funder
Japan Society for the Promotion of Science
Publisher
AIP Publishing
Subject
Physics and Astronomy (miscellaneous)
Link
https://aip.scitation.org/doi/pdf/10.1063/5.0057182
Reference37 articles.
1. Three-dimensional monolithic integration of III–V and Si(Ge) FETs for hybrid CMOS and beyond
2. Demonstration of 3-D SRAM Cell by 3-D Monolithic Integration of InGaAs n-FinFETs on FDSOI CMOS With Interlayer Contacts
3. Heterogeneous Integration of III–V Materials by Direct Wafer Bonding for High-Performance Electronics and Optoelectronics
4. Stackable InGaAs-on-Insulator HEMTs for Monolithic 3-D Integration
5. Accurate evaluation of specific contact resistivity between InAs/Ni–InAs alloy using a multi-sidewall transmission line method
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1. Heavily Doped Channel Carrier Mobility in β-Ga2O3 Lateral Accumulation MOSFET;IEEE Transactions on Electron Devices;2024-05
2. Low specific contact resistance between InAs/Ni–InAs evaluated by multi-sidewall TLM;AIP Advances;2023-05-01
3. Accurate evaluation of interface trap density at InAs MOS interfaces by using C–V curves at low temperatures;Japanese Journal of Applied Physics;2023-02-15
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