VLSI implementation of vedic multiplier and carry look ahead adder based FIR filter for denoising EEG signal
Author:
Publisher
AIP Publishing
Link
http://aip.scitation.org/doi/pdf/10.1063/5.0178693
Reference21 articles.
1. A.N. Snehi, A. Chouhan and V.K. Mishra, (2019) “VLSI Architecture for 2x2 and 3x3 fast parallel FIR filter using vedic multiplier and Koggee-stone Adder”, International Journal of Innovative Research in Science, Engineering and Technology, Vol. 8, pp. 2319–3753.
2. Design of Vedic multiplierbased FIR filter for signal processing applications
3. Low Area VLSI implementation of CSLA for FIR Filter Design
4. Design And Implementation of Combined Pipelining and Parallel Processing Architecture for FIR and IIR Filters Using VHDL
5. A New Cost-Aware Sensitivity-Driven Algorithm for the Design of FIR Filters
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