3D TCAD Modeling For Stress Management In Through Silicon Via (TSV) Stacks
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AIP
Cited by 17 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Stress Impact of the Annealing Procedure of Cu-Filled TSV Packaging on the Performance of Nano-Scaled MOSFETs Evaluated by an Analytical Solution and FEA-Based Submodeling Technique;Materials;2021-09-11
2. Analytical Heat Transfer Model for a TTSVs-based Thermal Mitigation Power Chip;JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE;2021-06-30
3. A Novel Lining Method for Eliminating Plastic Deformation and Protrusion of Copper in Cu-TSV Using FEM Analysis;Journal of Electronic Materials;2020-03-26
4. Evaluation of Cu-TSV Barrier Materials as a Solution to Copper Protrusion;Journal of Electronic Materials;2019-12-20
5. Modeling Copper Plastic Deformation and Liner Viscoelastic Flow Effects on Performance and Reliability in Through Silicon Via (TSV) Fabrication Processes;IEEE Transactions on Device and Materials Reliability;2019-12
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