Thermal optimization of two-terminal SOT-MRAM

Author:

Su Haotian1ORCID,Kwon Heungdong2ORCID,Hwang William1ORCID,Xue Fen1ORCID,Köroğlu Çağıl1ORCID,Tsai Wilman3,Asheghi Mehdi2,Goodson Kenneth E.23,Wang Shan X.13ORCID,Pop Eric1345ORCID

Affiliation:

1. Department of Electrical Engineering, Stanford University 1 , Stanford, California 94305, USA

2. Department of Mechanical Engineering, Stanford University 2 , Stanford, California 94305, USA

3. Department of Materials Science and Engineering, Stanford University 3 , Stanford, California 94305, USA

4. Department of Applied Physics, Stanford University 4 , Stanford, California 94305, USA

5. Precourt Institute for Energy, Stanford University 5 , Stanford, California 94305, USA

Abstract

While magnetoresistive random-access memory (MRAM) stands out as a leading candidate for embedded nonvolatile memory and last-level cache applications, its endurance is compromised by substantial self-heating due to the high programming current density. The effect of self-heating on the endurance of the magnetic tunnel junction (MTJ) has primarily been studied in spin-transfer torque (STT)-MRAM. Here, we analyze the transient temperature response of two-terminal spin–orbit torque (SOT)-MRAM with a 1 ns switching current pulse using electro-thermal simulations. We estimate a peak temperature range of 350–450 °C in 40 nm diameter MTJs, underscoring the critical need for thermal management to improve endurance. We suggest several thermal engineering strategies to reduce the peak temperature by up to 120 °C in such devices, which could improve their endurance by at least a factor of 1000× at 0.75 V operating voltage. These results suggest that two-terminal SOT-MRAM could significantly outperform conventional STT-MRAM in terms of endurance, substantially benefiting from thermal engineering. These insights are pivotal for thermal optimization strategies in the development of MRAM technologies.

Funder

National Science Foundation

Future of Semiconductors (FuSe) program

Partnerships for Innovation (PFI) program

Advanced Chip Engineering Design and Fabrication (ACED Fab) program

Stanford Nonvolatile Memory Technology Research Initiative

Publisher

AIP Publishing

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