Tri-gate junctionless transistors with electrostatically highly doped channel

Abstract

Multiple-gated junctionless transistors (JLTs) with an extremely simple structure and bulk-conduction-based operation could overcome fundamental problems with respect to short-channel effects for sub-3-nm technology nodes. In this paper, the performance of a tri-gate JLT with an electrostatically highly doped channel is demonstrated through numerical simulation. Unique characteristics previously reported in fabricated JLTs were exhibited by the tri-gate transistors with an additional bottom-gate bias (Vgb = 50 V), which induced an effectively highly doped state of the channel. The results of this study show the feasibility of producing impurity scattering-free JLTs for next-generation technology nodes.