The origin of memory window closure with bipolar stress cycling in silicon ferroelectric field-effect-transistors

Abstract

A comprehensive quantitative root cause study of defect evolution leading to memory window closure from a charge balance and charge trapping perspective throughout all phases of a Si channel Hf0.5Zr0.5O2 (HZO) ferroelectric field-effect-transistor (FEFET) is reported. Starting with the first write pulse, an excessive SiO2 interlayer field is revealed that triggers the creation of defect levels Dit in excess of 1015 cm−2 eV−1 at the HZO–SiO2 interface screening ferroelectric (FE) polarization while enabling FE switching. Under subsequent early bipolar fatigue cycling (up to 104 cycles), defect creation commences at the SiO2–Si interface due to the high injected hole fluence (0.39 C/m2) during each stress pulse causing negative bias instability (NBI), which shifts the threshold voltage of the erase state VT,ERS by −0.3 V with accrual of permanently captured charge Nit of up to +5 × 10−3 C/m2 (3 × 1012 cm−2). Subsequently, Nit NBI generation at the SiO2–Si interface accelerates reaching levels of +7 × 10−2 C/m2, locking both FEFET program and erase drain current vs gate–source-voltage (ID–VGS) characteristics in the FEFET on-state inducing memory window closure at 105 cycles while FE switching (switched polarization Psw = 0.34 C/m2) remains essentially intact. These findings guide the down-selection toward suitable semiconductor/FE systems for charge balanced, reliable, and high endurance FEFETs.