Border trap evaluation for SiO2/GeO2/Ge gate stacks using deep-level transient spectroscopy
Author:
Affiliation:
1. Interdisciplinary Graduate School of Engineering Sciences, Kyushu University, 6-1 Kasuga-koen, Kasuga, Fukuoka 816-8580, Japan
2. Global Innovation Center, Kyushu University, 6-1 Kasuga-koen, Kasuga, Fukuoka 816-8580, Japan
Funder
Japan Society for the Promotion of Science
Publisher
AIP Publishing
Subject
General Physics and Astronomy
Link
http://aip.scitation.org/doi/pdf/10.1063/1.5055291
Reference31 articles.
1. High-k/Ge MOSFETs for future nanoelectronics
2. Germanium CMOS potential from material and process perspectives: Be more positive about germanium
3. Germanium Based Field-Effect Transistors: Challenges and Opportunities
4. III–V/Ge channel MOS device technologies in nano CMOS era
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4. Defect Characterization in High‐Electron‐Mobility Transistors with Regrown p‐GaN Gate by Low‐Frequency Noise and Deep‐Level Transient Spectroscopy;physica status solidi (a);2021-07-29
5. Interface trap and border trap characterization for Al2O3/GeOx/Ge gate stacks and influence of these traps on mobility of Ge p-MOSFET;AIP Advances;2020-06-01
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