Design and FPGA implementation machine learning based steller matrix encryption and decryption for high throughput and low latency

Author:

Rajashekhar U.,Kumar K. Pradeep,Kumara M. Niranjana,Viswanath K.

Publisher

AIP Publishing

Reference17 articles.

1. FPGA Implementation of AES Algorithm for Image, Audio, and Video Signal

2. CRYSTALS-Kyber algorithm specification (version 2.0),” NIST PQC round 2, Tech. Rep., 2019. [Online]. Available: https://pq-crystals.org/kyber/data/kyber-specification-round2.pdf

3. T. Newe, M. Rao, D. Toal, G. Dooly, E. Omerdic, and A. Mathur, Efficient and High Speed FPGA Bump in the Wire Implementation for Data Integrity and Confidentiality Services in the IoT. Springer International Publishing, 2017, pp. 259–285.

4. Hussain and H. Jamal, “An Efficient High Throughput FPGA Implementation of AES for Multi-gigabit Protocols,” in Proc. 10th International Conference on Frontiers of Information Technology (FIT), Dec 2012, pp. 215–218.

5. Sapna Kumari. C., K.V Prasad, “A Novel S-box Generation of AES using Elliptic Curve Cryptography(ECC)”, International Journal of Innovative Technology and Engineering (IJITEE) ISSN: 2278-3075, Volume-8 Issue-4, February 2019

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