On the parallelization approaches for Intel MIC architecture-Reference-Cited by-同舟云学术

On the parallelization approaches for Intel MIC architecture

Published:2016 Issue: Volume: Page:
ISSN:0094-243X
Container-title:AIP Conference Proceedings
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Atanassov E.,Gurov T.,Karaivanova A.,Ivanovska S.,Durchova M.,Dimitrov D.

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Reference13 articles.

1. J. Jeffers and J. Reinders, Intel Xeon Phi Coprocessor High-Performance Programming (Morgan Kaufmann, Boston, 2013).

2. Intel xeon phi coprocessor instruction set architecture reference manual, https://software.intel.com/sites/default/files/forum/278102/327364001en.pdf.

3. Supercomputer Sites, http://top500.org/.

4. Monte Carlo and quasi-Monte Carlo methods

5. H. Niederreiter, Random Number Generation and Quasi-Monte Carlo Methods (Society for Industrial and Applied Mathematics, Philadelphia, PA, USA, 1992).

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