Stretchable silicon array with stretchability at 66.1% ± 2.9% and silicon areal coverage of 71.5% enabled by wafer-level microfabrication strategy

Abstract

High-performance and massive manufacturing are the key objectives of stretchable electronics manufacturing technology. However, the limitations of the current manufacturing technologies in terms of silicon areal coverage and stretchability impose the tradeoff between high-performance and massive manufacturing. This work proposes a silicon wafer-level microfabrication strategy to fabricate stretchable silicon arrays, leveraging the parylene microelectromechanical systems compatible microfabrication capability and the established mechanical analytical models of the 3D micro-Kirigami structure. This wafer-level fabrication strategy yielded monolithic stretchable silicon arrays with high silicon areal coverage (71.5%) and high stretchability (66.1% ± 2.9%). The mechanical analytical models suggest the potential for simultaneously increased Si areal coverage and stretchability by leveraging miniaturization capability. This technique holds immense promise for high-performance stretchable arrayed devices with shape-adaptivity for complex or dynamic surfaces.