1. Alhalabi, B.; Al-Sheraidah, A., “A novel low power multiplexer-based full adder cell,” Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on, vol.3, no., pp.1433,1436 vol.3, 2001.
2. Ashutosh Gupta and Kota Solomon Raju, “Design and Implementation of 32-bit Controller for Interactive Interfacing with Reconfigurable Computing Systems” International Journal of Computer Science and Information Technology (IJCSIT), Vol.1, No.2, pp 80–87, Nov 2009. ISSN: 0975-3826(online); 0975-4660
3. Gupta, A., Duhan, M., & Raju Kota, S. (2009). HDL Implementation of Sine-Cosine Function Using CORDIC Algorithm in 32-Bit Floating Point Format. The Icfai University Journal of Science & Technology, 5(2), 40–48.
4. Sharma P and Gupta A. (2009), “Design, Implementation and Optimization of Highly Efficient UART”, The IUP Journal of Science and technology, Vol: 5, No. 4, pp. 21–30.
5. Bishwajeet Pandey and Manisha Pattanaik, “Clock Gating Aware Low Power ALU Design and Implementation on FPGA”, International Journal of Future Computer and Communication (IJFCC), Vol.2(5):461–465 ISSN: 2010-3751