JHDL - An HDL for Reconfigurable Systems
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Cited by 24 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. PyHDL-Eval: An LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs;Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD;2024-09-09
2. Encoder-based Many-Pattern Matching on FPGAs;2022 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS);2022-04-20
3. Design of a DSL for Converting Rust Programming Language into RTL;Advances in Internet, Data and Web Technologies;2020
4. COLDVL: a virtual laboratory tool with novel features to support learning in logic design and computer organisation;Journal of Computers in Education;2017-08-29
5. A Survey of High Level Synthesis Languages, Tools, and Compilers for Reconfigurable High Performance Computing;Advances in Intelligent Systems and Computing;2014
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