Design and Implementation of FPGA Based LogSig and TanSig Transfer Functions in IQ-Math Number Standard

Abstract

Artificial Neural Networks (ANNs) have been used extensively in engineering fields where many processes such as optimization, prediction, signal processing, decision making and control today. Transfer Functions (TF) used in these operations affect directly the output of the result by affecting the ANN structure. In the first stage of this study, apart from the studies in the literature, non-linear LogSig and TanSig TF have been coded using VHDL in accordance with the 32-bit (16I-16Q) IQ-Math standard. The exponential function e^n, which is common to these two TF structures, has been designed using the CORDIC-LUT approach. In the second stage, an FPGA-based sample three-input-three-output ANN has been performed. 8 neurons have been used in the hidden layer of this design. LogSig and TanSig TF have been used in the hidden layer and PureLin TF has been used in the output layer. The sample ANN has been coded using VHDL with 32-bit IQ-Math standard for two different TF. A separate testbench file has been created for each design, and all these designs have been tested using VHDL with the Xilinx ISE DS. For the simulation results obtained, MSE and RMSE error analyzes were performed using numerical-based LogSig-TanSig TF and ANN designs, and the results were presented. Then, each design has been synthesized for the XC7K70T-3FBG676 FPGA (Kintex-7), and the chip statistics have been presented by performing the Place-Route process. As a result, ANN-LS (Artificial Neural Networks-LogSig) design produced more successful results with 8.86E-06 MSE and 2.98E-03 RMSE error analysis results. In future studies, real-time ANN applications can be realized on FPGA chips by using these ANN and TF designs.