Separation of Input Variables for Optimization of the Mealy FSM Circuit

Abstract

Introduction. One of the most important blocks of almost any digital system is the control device (CU), since the characteristics of the CU largely determine the characteristics of the system as a whole. In the practice of engineering design, the behavior of the CU is often specified using the Mealy finite state machine (FSM) model. A feature of Mealy FSM is the dependence of systems of Boolean functions that define the circuit on FSM inputs and states. In this article, this feature is taken into account when optimizing the characteristics of FSM circuit in the basis of FPGA chips. When developing FSM circuits, it is necessary to optimize its characteristics, such as performance and hardware costs. FPGAs are one of the most common logic bases for implementing digital systems. FPGA components such as look-up table (LUT) elements, programmable flip-flops, embedded memory blocks (EMBs), and programmable interconnects are sufficient to implement the CU circuit. The purpose of the article. In this paper, we propose a method for reducing hardware costs in the Mealy FSM cirucit implemented in the FPGA basis. In this case, the problem of implementing a circuit in a mixed elemental basis is considered. A mixed basis is understood as the joint use of LUTs and EMBs. The situation is considered when the number of available EMBs is extremely limited, which is quite possible, since EMBs are widely used to implement various operating blocks of digital systems. The main disadvantage of LUTs is the small number of inputs. Modern digital systems can generate signals of logical conditions entering the CU, the number of which is tens of times greater than the number of LUT inputs. This discrepancy between the characteristics of the control algorithm and the number of inputs of the LUTs leads to multilevel CU circuits with an irregular structure of programmable interconnections. To optimize multilevel schemes, the method of replacing input variables is used with the joint use of LUTs and EMB blocks. Results. The analysis of the effectiveness of the proposed method was carried out using the libraries of standard benchmarks FSMs and the Vivado CAD platform. Studies have shown that the proposed method makes it possible to reduce the number of LUTs in the range from 100% to 82%. For 37% of automata, the method of replacing input variables can be applied only in conjunction with the separation of input variables. Conclusions. The proposed method makes it possible to reduce hardware costs (the number of LUTs and their interconnections), delay time, and power consumption. The article shows the conditions for applying the proposed method. The results of studies of the effectiveness of the proposed method for standard automata using chips of the Virtex-7 family and the Vivado industrial package are presented. Keywords: finite state machine, synthesis, FPGA, EMB, LUT, input replacement.