Abstract
With the miniaturization of transistors, the current leakage also increases due to the increasing tunnelling effect. Plus, Boltzmann’s tyranny limits the subthreshold swing to be best and ideal at 60 mV/decade. Due to these, the power consumption in transistors keeps soaring up. Therefore, in this paper, the Negative Capacitance Effect Field Transistor (NCFET) is discussed as it possesses excellent potentials in reducing the power consumption in transistors. The negative capacitance induced in NCFET enables the internal voltage amplification and reduces the required voltage for the transistor to operate, and therefore, the power consumption is reduced. The literature reviews are done to gain knowledge on the structure and behavior of the NCFET. Next, the process and device simulation of NMOS are studied using Silvaco TCAD to get the idea of developing a circuit simulator model of NCFET. After that, we developed the circuit model of NCFET and MOSFET. Next, the ferroelectric parameters are varied to study how it will affect the ferroelectric material's polarization and capacitance. The ferroelectric thickness and source-drain doping concentration of the proposed NCFET model is also varied to study the NCFET behaviors in peak current, subthreshold slope, saturation current and saturation slope. Lastly, the performances of NCFET and MOSFET are compared. It is found that the NCFET has better performance as compared to the MOSFET as the NCFET can achieve a steeper subthreshold slope.