An Implementation of a Grid Square Codes Generator on a RISC-V Processor
Author:
Affiliation:
1. Yamagata University
2. Yamagata College of Industry and Technology
Publisher
IJNC Editorial Committee
Subject
General Medicine
Link
https://www.jstage.jst.go.jp/article/ijnc/12/1/12_204/_pdf
Reference6 articles.
1. [1] A. Waterman and K. Asanovic, The RISC-V Instruction Set Manual Volume I: User-Level ISA Document Version2.2, RISC-V Foundation, 2017.
2. [2] Statistics Bureau of Japan, Method of Demarcation for Grid Square, [online] Available: http://www.stat.go.jp/english/data/mesh/05.html.
3. [3] A. Sato, S. Nishimura and H. Tsubaki, World Grid Square codes: Definition and an example of World Grid Square data, 2017 IEEE Int. Conf. on Big Data (BIGDATA), pp. 4156-4165, Dec. 2017.
4. [4] M. Gautschi et al., Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25(10), pp. 2700–2713, 2017.
5. [5] F. Zaruba and L. Benini, The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29(11), pp. 2629–2640, 2019.
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