Bounded model checking for fixed-point digital filters
Author:
Funder
CNPq
FAPEAM
Publisher
Springer Science and Business Media LLC
Subject
General Computer Science
Link
http://link.springer.com/article/10.1186/s13173-016-0041-8/fulltext.html
Reference67 articles.
1. Institute of Electrical and Electronics Engineers (2008) IEEE standard for floating-point arithmetic (IEEE Std 754-2008). IEEE, New York.
2. Proakis JG, Manolakis DG (1996) Digital signal processing: principles, algorithms, and applications. Prentice Hall, Upper Saddle River.
3. Parker SR, Hess SF (1971) Limit-cycle oscillations in digital filters. IEEE Trans Circuit Theory 18(6): 687–697.
4. Bauer P, Leclerc LJ (1991) A computer-aided test for the absence of limit cycles in fixed-point digital filters. IEEE Trans Signal Process 39(11): 2400–2410.
5. Shafic EM, Sandberg IW (1995) A study of bounds on limit cycles in digital filters. Circ Syst Signal Process 14(6): 725–734.
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