1. Chakraborty K, Roy S (2012) Architecturally homogeneous power-performance heterogeneous multicore processor. US Patent App. 13/495,961. (Online). https://www.google.com/patents/US20120324250
2. (2012) The ITRS Technology Working Groups, International Technology Roadmap for Semiconductors (ITRS). (Online) http://www.itrs.net/ITRS%201999-014%20Mtgs,%20Presentations%20&%20Links/2013ITRS/2013Chapters/2013ExecutiveSummary.pdf. Accessed 2013
3. Vijayalakshmi S, Anpalagan A, Woungang I, Kothari D (2013) Power management in multi-core processors using automatic dynamic pipeline stage unification. In: 2013 International Symposium on Performance Evaluation of Computer and Telecommunication Systems (SPECTS), July 2013, pp 120–127
4. Kunkel SR, Smith JE (1986) Optimal pipelining in supercomputers. In: Proceedings of the 13th annual international symposium on Computer architecture, ser. ISCA ’86. IEEE Computer Society Press, Los Alamitos, pp 404–411. (Online). http://dl.acm.org/citation.cfm?id=17407.17403
5. Hartstein A, Puzak TR (2002) Optimum Power/Performance Pipeline Depth. In: IEEE Computer Society, IBM-T. J. Watson Research Center