Design of GAA Nanosheet Ferroelectric Area Tunneling FET and Its Significance with DC/RF Characteristics Including Linearity Analyses

Abstract

AbstractThis work reports an emerging structure of gate-all-around ferroelectric area tunneling field-effect transistor (FATFET) by considering ferroelectric and a n-epitaxial layer enveloped around the overlapped region of the source and channel to succeed with complete area of tunneling probability. To accomplish this, ferroelectric ($$\hbox{Hf}_{0.5}\hbox{Zr}_{0.5}\hbox{O}_2$$ Hf 0.5 Zr 0.5 O 2 ) is exploited and modeled to boost the FATFET performance through internal-voltage ($$V_{{\rm int}}$$ V int ) amplification. The corresponding modeling approach to estimate the ferroelectric parameters along with $$V_{{\rm int}}$$ V int calculations of the metal-ferroelectric-insulator (MFIS) option through capacitance equivalent method is addressed. Using these options the proposed device outperforms effectively in delivering superior DC and RF performance among possible options of the $$\hbox{Si}_{1-x}\hbox{Ge}_x$$ Si 1 - x Ge x ferroelectric TFETs. The significance of proposed design is examined with recently reported ferroelectric TFETs. Our results show 10-time advancement on the $$I_{{\rm on}}$$ I on , reduced steep or average subthreshold swing (< 25 mV/dec), frequencies higher than 150 GHz, and insignificant to linearity deviations at low bias points. Furthermore, 2-order reduction in energy efficiency is succeeded with the proposed design environment.